View MX604_8169674.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data bulletin MX604 v.23 compatible modem 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. preliminary information features applications 1200bps forward, 75bps back channels conforms to relevant sections of v.23 and etsi specifications line equalization 1200bps data retiming facility can eliminate external uart low voltage operation (3.3 to 5.0v) low power operation 1ma typ. @ 3.3v operating mode 1 a typ. zero-power mode standard 3.58mhz xtal/clock telephone telemetry system applications c data control status MX604 line interface telephone line the MX604 is a low voltage, low power cmos device, used for the reception or transmission of asynchronous 1200bps data and full-duplex 75bps back channel data in accordance with ccitt v.23 and etsi specifications. this device provides an optional tx and rx data retiming function which can eliminate, based on user preference, the need for an external uart when operating at 1200bps. the device can disable the back channel or be operated so only the mark or space tone is produced. the optional line equalizer is incorporated into the receive path and is controlled by an external logic level. the MX604 may be used in a wide range of telephone telemetry systems. low voltage capability, a low operating current (1ma typ. @ v dd = 3.3v), and a very low current 'sleep' mode (1 a typ.) make the MX604 ideal for both portable terminal and line powered applications. the MX604 is available in the following packages: 24-pin tssop (MX604tn), 16-pin soic (MX604dw) and 16-pin pdip (MX604p).
v.23 compatible modem 2 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. contents section page 1. block diagram .......................................................................................................... 3 2. signal list ................................................................................................................. 4 3. external components .............................................................................................. 5 4. general description ................................................................................................. 5 4.1 xtal osc and clock dividers ................................................................................................. .. 5 4.2 mode control logic .......................................................................................................... ...... 6 4.3 rx input amplifier .......................................................................................................... ......... 6 4.4 receive filter and equalizer................................................................................................ ... 6 4.5 energy detector............................................................................................................. ......... 7 4.6 fsk demodulator ............................................................................................................. ...... 7 4.7 fsk modulator and transmit filter......................................................................................... 7 4.8 rx data retiming ............................................................................................................ ....... 9 4.9 tx data retiming............................................................................................................ ...... 10 5. application .............................................................................................................. 11 5.1 line interface.............................................................................................................. .......... 11 6. performance specification .................................................................................... 12 6.1 electrical performance ...................................................................................................... ... 12 6.2 timing...................................................................................................................... ............. 15 6.3 packaging................................................................................................................... .......... 16 mx com, inc. reserves the right to change specifications at any time and without notice
v.23 compatible modem 3 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 1. block diagram txd m0 rxeq clk rxd rdy m1 det energy detect fsk de-modulator receive filter and equalizer mode control logic rx/tx data re-timing transmit filter and output buffer fsk modulator rxin rxampout txout xtal osc and clock dividers xtal/ clock xtal v dd v bias v bias v ss figure 1: block diagram
v.23 compatible modem 4 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 2. signal list pin no. name type description p, dw tn 1 1 xtal output output of the on-chip xtal oscillator inverter. 2 2 xtal/clock input input to the on-chip xtal oscillator inverter. 3 5 m0 input a logic level input for setting the mode of the device. see section 4.2 4 6 m1 input a logic level input for setting the mode of the device. see section 4.2 5 7 rxin input input to the rx input amplifier. 6 8 rxampout output output of the rx input amplifier. 7 11 txout output output of the fsk generator. 8 12 v ss power negative supply (ground). 9 13 v bias output internally generated bias voltage, held at v dd /2 when the device is not in 'zero-power' mode. should be decoupled to v ss by a capacitor mounted close to the device pins. 10 14 rxeq input a logic level input for enabling/disabling the equalizer in the receive filter. see section 4.4 11 17 txd input a logic level input for either the raw input to the fsk modulator or data to be re-timed depending on the state of the m0, m1 and clk inputs. see section 4.9 12 18 clk input a logic level input which may be used to clock data bits in/out of the fsk data retiming block. 13 19 rxd output a logic level output carrying either the raw output of the fsk demodulator or re-timed characters depending on the state of the m0, m1 and clk inputs. see section 4.8 14 20 det output a logic level output of the on-chip energy detect circuit. 15 23 rdy output "ready for data transfer" output of the on-chip data retiming circuit. this open-drain active low output may be used as an interrupt request/wake-up input to the associated c. an external pull-up resistor should be connected between this output and v dd . 16 24 v dd power the positive supply rail. levels and thresholds within the device are proportional to this voltage. should be decoupled to v ss by a capacitor mounted close to the device pins. 3, 4, 9, 10 ,15, 16, 21, 22 n/c no internal connections this device is capable of detecting and decoding small amplitude signals. achieving the v dd and v bias decoupling and protection of the receive path from extraneous in-band signals is very important. it is recommended that decoupling capacitors be placed so the connection between them and the device pins is as short as possible. a ground plane protecting the receive path will help attenuate interfering signals.
v.23 compatible modem 5 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 3. external components v dd v bias v ss MX604 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 det rdy clk rxeq rxd txd m1 txout rxampout rxin m0 to / fr o m c from c c1 c2 c3 c4 x1 r1 xtal/clock xtal v dd r1 100k 5%, c1, c2 18pf 10% c3 0.1 f 10% c4 0.1 f 10% x1 note 1 3.579545mhz figure 2: recommended external components for typical application external components notes: 1. a crystal frequency of 3.579545mhz 0.1% is required for correct fsk operation. for best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of v dd , peak-peak. tuning fork crystals generally cannot meet this requirement. to obtain crystal oscillator design assistance, consult your crystal manufacturer. operation of this device without a xtal or clock input may cause device damage. 4. general description 4.1 xtal osc and clock dividers frequency and timing accuracy of the MX604 is determined by a 3.579545mhz clock present at the xtal/clock pin. this may be generated by the on-chip oscillator inverter using the external components c1, c2 and x1 of figure 2, or it may be supplied from an external source to the xtal/clock input. if supplied from an external source, c1, c2 and x1 should not be used. the on-chip oscillator is disabled in the 'zero-power' mode. if the clock is provided by an external source which is not always running, then the 'zero-power' mode must be set when the clock is not available. failure to observe this rule may cause a significant rise in the supply current drawn by MX604 as well as generating undefined states of the rxd, det and rdy outputs.
v.23 compatible modem 6 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 4.2 mode control logic the MX604's operating mode is determined by the logic levels applied to the m0 and m1 input pins: m1 m0 rx mode tx mode data retime [1] 0 0 1200bps 75bps rx 0 1 off 1200bps tx 1 0 1200bps off rx 1 1 'zero-power' - [1] if enabled. note: on applying power to the device the mode must be set to 'zp', i.e. m0=1, m1=1, until v dd has stabilized. in the 'zero-power' mode, power is removed from all internal circuitry. when leaving 'zero-power' mode there must be a 20ms delay before any tx data is passed to, or rx data read from, the device to allow the bias level, filters and oscillator to stabilize. 4.3 rx input amplifier the rx input amplifier is used to adjust the signal received to the correct amplitude for the fsk receiver and energy detect circuits (see section 5.1). 4.4 receive filter and equalizer the receive filter and equalizer is used to attenuate out of band noise and interfering signals, especially the locally generated 75bps transmit tones which might otherwise reach the 1200bps fsk demodulator and energy detector circuits. this block also includes a switchable equalizer section. when the rxeq pin is low the overall group delay of the receive filter is flat over the 1200bps frequency range. if the rxeq pin is high the receive filter's typical overall group delay will be as shown in figure 3. -0.15 -0.125 -0.1 -0.075 -0.05 -0.025 0 0.025 500 1000 1500 2000 2500 delay/ms frequency/hz figure 3: rx equalizer group delay (rxeq = 1) with respect to 1700hz
v.23 compatible modem 7 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 4.5 energy detector the energy detector block operates by measuring the level of the signal at the output of the receive filter, and comparing it against a preset threshold. the det output will be set high when the level has exceeded the threshold for a sufficient time. amplitude and time hysteresis are used to reduce chattering of the det output in marginal conditions. note: this circuit may also respond to non-fsk signals such as speech. det line signal m0, m1 fsk receive mode fsk signal te on te off see section 6.1 for definitions of te on and te off figure 4: fsk level detector operation 4.6 fsk demodulator the fsk demodulator block converts the 1200bps fsk input signal to a logic level received data signal which is output via the rxd pin as long as the data retiming function is not enabled (see section 4.8). this output does not depend on the state of the det output. when the rx 1200bps mode is 'off' or in 'zp' the det and rxd pins are held low. note: in the absence of a valid fsk signal, the demodulator may falsely interpret speech or other extraneous signals as data. for this reason it is advised that the rxd pin be read only when data is expected. 4.7 fsk modulator and transmit filter the fsk modulator and transmit filter blocks produce a tone according to the txd, m0 and m1 inputs as shown in the table below, assuming data retiming is not being used: m1 m0 txd = 0 txd = 1 11 - 10 0hz [1] 0 0 450hz 390hz 0 1 2100hz 1300hz fsk modulator and transmit filter note: [1] txout held at approx. v dd /2. when modulated at the appropriate baud rates, the transmit filter and associated external components (see section 5.1) limit the fsk out of band energy sent to the line in accordance with figure 5 and figure 6, assuming that the signal on the line is at -6dbm or less.
v.23 compatible modem 8 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. -70 -60 -50 -40 -30 dbm -10 0 10 frequency/ hz 1000 10000 100000 1300 hz 3400 hz 28 khz 100 -20 figure 5: tx limits at 75bps rate -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 dbm frequency / hz 450 hz 3400 hz 28 khz figure 6: tx limits at 1200bps rate
v.23 compatible modem 9 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 4.8 rx data retiming the rx data retiming function may be used when the received data consists of 1200bps asynchronous characters, each character consisting of one start bit followed by a minimum of 9 formatted bits as shown in the table below. data bits parity bits stop bits 70 2 71 1 80 1 81 1 90 1 when enabled in receive mode, the data retiming block extracts the first 9 bits of each character following the start bit, from the received asynchronous data stream, and presents them to the c, under the control of strobe pulses applied to the clk input. the timing of these pulses is not critical. they may be generated easily by a simple software loop. this facility removes the need for a uart in the c without incurring an excessive software overhead. the receive retiming block consists of two 9-bit shift registers, the input of the first is connected to the output of the fsk demodulator and the output of the second is connected to the rxd pin. the first register is clocked by an internally generated signal that stores the 9 received bits following the timing reference of a high to low transition at the output of the fsk demodulator. when the 9th bit is clocked into the first register these 9 bits are transferred to the second register, a new stop-start search is initiated and the clk input is sampled. if the clk input is low at this time the rdy pin is pulled low and the first received bit is output on the rxd pin. the clk pin should then be pulsed high 9 times, the first 8 high to low transitions will be used by the device to clock out the bits in the second register. the rdy output is cleared the first time the clk input goes high. at the end of the 9th pulse the rxd pin will be connected to the fsk demodulator output. to use the data retiming function, the clk input should be kept low until the rdy output goes low; if the data retiming function is not required then the clk input should be kept high at all times. the only restrictions on the timing of the clk waveform are those shown in figure 7 and the need to complete the transfer of all nine bits into the c within the time of a complete character at 1200bps. start stop 1 1 2 345678 9 9 fsk demod output : rdy output : rxck input : rxd output : received character 'n' retimed data bits from received character 'n' data bit 1 data bit 2 t d tc hi tc lo rxck rxd 9 bits of data t d t d rdy t d = internal MX604 delay, tc hi = clk high time, tc lo = clk low time figure 7: fsk operation with rx data re-timing note: if enabled, the data retiming block may interpret speech or other signals as random characters.
v.23 compatible modem 10 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. if the data retiming facility is not required, the clk input to the MX604 should be kept high at all times. the asynchronous data from the fsk demodulator will then be connected directly to the rxd output pin, and the rdy output will not be activated by the fsk signal. this case is illustrated by the example in figure 8 start start stop stop 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 fsk demod output : rxd output : received character 'n' figure 8: fsk operation without rx data re-timing (clk always high) 4.9 tx data retiming the tx data retiming block, when enabled in 1200bps transmit mode, requires the controlling c to load 1 bit at a time into the device by a pulse applied to the clk input. the timing of this pulse is not critical. it may be generated easily by a simple software loop. this facility removes the need for a uart in the c without incurring an excessive software overhead. the tx retiming circuit consists of two 1-bit registers in series, the input of the first is connected to the txd pin and the output of the second feeds the fsk modulator. the second register is clocked by an internally generated 1200hz signal and when this occurs the clk input is sampled. if the clk input is high the txd pin directly controls the fsk modulator, if the clk input is low the fsk modulator is controlled by the output of the second register and the rdy pin is pulled low. the rdy output is reset by a high level on the clk input pin. a low to high change on the clk input pin will latch the data from the txd input pin into the first register ready for transfer to the second register when the internal 1200hz signal next occurs. to use the retiming option, the clk input should be held low until the rdy output is pulled low. when the rdy pin goes low, the next data bit should be applied to the txd input and the clk input pulled high and then low within the time limits defined in figure 9. 1 1 1 2 3 4 3 2 fsk modulator input : clk input : txd input : t s t h t d t r tc hi rdy clk txd rdy output : t d = internal MX604 delay; t r = low to clk going low; t s = data set up time tc hi = clk high time, t h = data hold time figure 9: fsk operation with tx data retiming to ensure synchronization between controlling device and the MX604 when entering tx retiming mode the txd pin must be held at a constant logic level from when the clk pin is first pulled low to the end of loading in the second retimed bit. similarly when exiting tx retiming mode the txd pin should be held at the same logic level as the last retimed bit for at least 2 bit times after the clk line is pulled high.
v.23 compatible modem 11 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. if the data retiming facility is not required, then the clk input to the MX604 should be kept high at all times. the asynchronous data to the fsk modulator will then be connected directly to the txd input pin. this is illustrated in figure 10 and will also be the case when transmitting 75bps data which has no retime option. n-2 n-2 n-1 n-1 n n n+1 n+1 n+2 n+2 fsk modulator input : txd input : figure 10: fsk operation without tx data re-timing (clk always high) 5. application 5.1 line interface the signals on the telephone line are not suitable for direct connection to the MX604. a line interface circuit is necessary to: provide high voltage and dc isolation attenuate the tx signal present at the rx input provide the low impedance drive necessary for the line filter the tx and rx signals line 1:1 r3 r6 r5 r4 z r7 rxin rxampout txout v bias a b c a2 a1 0v c5 c6 c7 r2 + r2 see notes 1%, c5 22 f 20% r3 see notes 1%, c6 100pf 10% r4-r7 100k 1%, c7 330pf 10% figure 11: line interface circuit
v.23 compatible modem 12 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. line interface notes: the components 'z' between points b and c should match the line impedance. device a2 must be able to drive 'z' and the line. r2: for optimum results r2 should be set so that the gain is v dd /5.0, i.e. r2 = 100k at v dd = 5.0v, rising to 150k at v dd = 3.3v. r3: the levels in db (relative to a 775mv rms signal) at 'a', 'b' and 'c' in the line interface circuit are: 'a' = 20log(v dd /5) 'b' = 'a' + 20log(100k /r3) 'c' = 'b' - 6 v dd 'a' r3 'b' 'c' 3.3v -3.6db 100k -3.6db -9.6db 5.0v 0db 150k -3.5db -9.5db 6. performance specification 6.1 electrical performance absolute maximum ratings exceeding these maximum ratings can result in damage to the device. general min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current v dd -30 30 ma v ss -30 30 ma any other pins -20 20 ma dw / pdip package total allowable power dissipation at t amb = 25c 800 mw derating above 25c 13 mw/c above 25c storage temperature -55 125 c operating temperature -40 85 c operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss )3.05.5v temperature -40 85 c xtal frequency 1 3.575965 3.583125 mhz operating limits notes: 1. a crystal frequency of 3.579545mhz 0.1% is required for correct fsk operation.
v.23 compatible modem 13 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. operating characteristics for the following conditions unless otherwise specified: v dd = 3.3v at t amb = 25c xtal frequency = 3.579545mhz 0.1%, 0dbv corresponds to 1.0v rms, 0db = 0dbm = 775mv rms into 600 . notes min. typ. max. units dc parameters i dd (m0='1', m1='1') 1, 2 1 a i dd (m0 or m1='0') at v dd = 3.0v 1 1.0 1.25 ma i dd (m0 or m1='0') at v dd = 5.0v 1 1.7 2.5 ma logic '1' input level 70% v dd logic '0' input level 30% v dd logic input leakage current (v in = 0 to v dd ), excluding xtal/clock input -1.0 1.0 a output logic '1' level (l oh = 360 a) v dd -0.4 v output logic '0' level (l ol = 360 a) 0.4 v output 'off' state current (v out = v dd )1.0 a fsk demodulator bit rate 0 1200 1212 baud mark (logical 1) frequency 1280 1300 1320 hz space (logical 0) frequency 2068 2100 2132 hz valid input level range 3 -40.0 -8.0 dbv acceptable twist (mark level wrt space level) -7.0 7.0 db acceptable signal to noise ratio 4 20.0 db level detector 'on' threshold level 3 -40.0 dbv level detector 'off' to 'on' time (figure 4 te on ) 25.0 ms level detector 'on' to 'off' time (figure 4 te off )8.0 ms fsk retiming acceptable rx data rate 1188 1200 1212 baud tx data rate 1194 1206 baud fsk modulator txout level 5 -1.0 0 1.0 db twist (mark level wrt space level) -2.0 0 2.0 db 1200bps (m1='0', m0='1'). bit rate 0 1200 1212 baud mark (logical 1) frequency 1297 1303 hz space (logical 0) frequency 2097 2103 hz 75bps (m1='0', m0='0'). bit rate 0 75 76 baud mark (logical 1) frequency 388 392 hz space (logical 0) frequency 448 452 hz
v.23 compatible modem 14 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. notes min. typ. max. units input amplifier impedance (rxin pin) 6 10.0 m voltage gain 6 500 v/v xtal/clock input 'high' pulse width 7 100 ns 'low' pulse width 7 100 ns operating characteristics notes: 1. not including any current drawn from the MX604 pins by external circuitry other than x1, c1 and c2. 2. txd, rxeq and clk inputs at v ss , m0 and m1 inputs at v dd . 3. measured at the rx input amplifier output (pin rxampout) for 1300hz and v dd = 5.0v. the internal threshold levels are proportional to v dd . to cater for other supply voltages or different signal level ranges the voltage gain of the rx input amplifier should be adjusted by selecting the appropriate external components as described in section 5.1 4. flat noise in 300-3400hz band. 5. relative to 775mv rms with v dd = 5.0v for load resistance greater than 40k . 6. open loop, small signal low frequency measurements. 7. timing for an external input to the xtal/clock pin.
v.23 compatible modem 15 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.2 timing data and mode timing notes min. typ. max. units rx data delay (rxin to rxd) 1, 5 2.55 ms tx delay data (txd to txout) 1, 6 0.1 ms mode change delay zp to tx or rx 2 20 ms mode change delay tx1200 to rx1200 2 4.0 ms mode change delay rx1200 to tx1200 2 0.2 ms t d = internal MX604 delay 3, 4 1 s tc hi = clk high time 3, 4 1 s tc lo = clk low time 3 1 s t r = rdy low to clk going low 4 800 s t s = data set-up time 4 1 s t h = data hold time 4 1 s timing notes 1. when data retiming is not enabled. 2. delay from mode change to reliable data at txout or rxd pins. 3. reference figure 7. 4. reference figure 9. 5. reference figure 12. 6. reference figure 13. valid 1 or 0 rxd rxin (fsk signal) rx data delay note: m0 and m1 are preset and stable. figure 12: rxin to rxd delay time txd txout (fsk signal) tx data delay f hi f lo f lo f hi note: m0 and m1 are preset and stable. f lo and f hi are the two fsk signaling frequencies. figure 13: txd to txout delay time
v.23 compatible modem 16 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.3 packaging pin 1 a b p j y alternative pin location marking e l x t w c k h z note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e h typ. max. min. dim. j p x w t y k l 0.105 (2.67) 0.093 (2.36) 0.419 (10.64) 45 7 0 10 0.050 (1.27) 0.041 (1.04) 0.413 (10.49) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.390 (9.90) 0.020 (0.51) 0.003 (0.08) 0.009 (0.23) 0.0125 (0.32) 0.013 (0.33) 0.020 (0.51) 0.395 (10.03) 0.286 (7.26) z 5 5 figure 14: 16-pin soic mechanical outline: order as part no. MX604dw package tolerances typ. max. min. a b c e e1 h dim. j j1 p y t k l 0.200 (5.06) 0.262 (6.63) 0.390 (9.91). 7 0.150 (3.81) 0.810 (20.57) 0.135 (3.43) 0.100 (2.54) 0.121 (3.07) 0.300 (7.62) 0.290 (7.37) 0.325 (8.26) 0.015 (0.38) 0.070 (1.77) 0.008 (0.20) 0.015 (0.38) 0.014 (0.35) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.056 (1.42) 0.064 (1.63) 0.740 (18.80) 0.240 (6.10) b a pin 1 e y e1 t k h j1 j c p l note: all dimensions in inches (mm.) angles are in degrees figure 15: 16-pin pdip mechanical outline: order as part no. MX604p
v.23 compatible modem 17 MX604 preliminary information 1998 mx com, inc. tele: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480152.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. pin 1 a b alternative pin location marking e l t p j y c h 0.303 (7.70) package tolerances typ. max. min. a b c e h dim. j p y t l 0.047 (1.20) ---------- 0.256 (6.50) 0 8 0.030 (0.75) 0.311 (7.90) 0.177 (4.50) 0.0256 (0.65) 0.020 (0.50) 0.248 (6.30) 0.006 (0.15) 0.002 (0.05) 0.003 (0.08) 0.008 (0.20) 0.007 (0.17) 0.012 (0.30) 0.169 (4.30) note : all dimensions in inches (mm.) angles are in degrees figure 16: 24-pin tssop mechanical outline: order as part no. MX604tn

▲Up To Search▲

Price & Availability of MX604

	To Download MX604 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .